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K1B6416B6C
Document Title
4Mx16 bit Synchronous Burst Uni-Transistor Random Access Memory
UtRAM
Revision History
Revision No. History
0.0 Initial Draft - Design target Revised - Deleted Deep Power Down Mode support Revised - Changed product code from K1B6416B7C into K1B6416B6C
Draft Date
March 11, 2004
Remark
Advance
0.1
April 19, 2004
Advance
0.2
May 10, 2004
Advance
0.3
Revised September 1, 2004 Preliminary - Filled out Package type(54ball FBGA 6.0mm x 8.0mm) - Changed Hi-Z parameters(tCHZ, tOHZ, tBHZ, tWZ) from Max.7ns into Max.12ns and changed tHZ from Max.10ns into Max.12ns - Updated "Fig.17 TIMING WAVEFORM OF WRITE CYCLE(1)" in page 23 - Added comment on standby current(ISB1) measure condition as "Standby mode is supposed to be set up after at least one active operation after power up. ISB1 is measured after 60ms from the time when standby mode is set up." - Added comment on restriction of the transition between Asynchronous Write operation and Fully Synchronous bus operation(Page 10,11) - Filled out ISB1 value, ISBP value and ICC2 value in Table 17(DC AND OPERATING CHARACTERISTICS) - Added Synchronous Operating Current(ICC3, Max.40mA) - Added tCSHP(A)(CS high pulse width) parameter as Min.10ns in the ASYNCHRONOUS AC CHARACTERISTICS Revised October 12, 2004 - Changed ISB1(< 40C) and ISBP(3/4 block, < 40C) from 100A into 120A - Changed ISBP(1/2 block and 1/4 block, < 40C) from 95A into 115A Finalized January 20, 2005 Preliminary
0.4
1.0
Final
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
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K1B6416B6C
4M x 16 bit Synchronous Burst Uni-Transistor CMOS RAM
FEATURES
* * * * * * *
UtRAM
GENERAL DESCRIPTION
The world is moving into the mobile multi-media era and therefore the mobile handsets need much bigger memory capacity to handle the multi-media data. SAMSUNG's UtRAM products are designed to meet all the request from the various customers who want to cope with the fast growing mobile market. UtRAM is the perfect solution for the mobile market with its low cost, high density and high performance feature. K1B6416B6C is fabricated by SAMSUNGs advanced CMOS technology using one transistor memory cell. The device supports the traditional SRAM like asynchronous bus operation(asynchronous page read and asynchronous write), the NOR flash like synchronous bus operation(synchronous burst read and asynchronous write) and the fully synchronous bus operation(synchronous burst read and synchronous burst write). These three bus operation modes are defined through the mode register setting. The device also supports the special features for the standby power saving. Those are the Partial Array Refresh(PAR) mode and internal Temperature Compensated Self Refresh(TCSR) mode. The optimization of output driver strength is possible through the mode register setting to adjust for the different data loadings. Through this driver strength optimization, the device can minimize the noise generated on the data bus during read operation.
Process Technology: CMOS Organization: 4M x16 bit Power Supply Voltage: 1.7~2.0V Three State Outputs Supports MRS (Mode Register Set) MRS control - MRS Pin Control Supports Power Saving modes - Partial Array Refresh mode Internal TCSR * Supports Driver Strength Optimization for system environment power saving. * Supports Asynchronous 4-Page Read and Asynchronous Write Operation * Supports Synchronous Burst Read and Asynchronous Write Operation(Address Latch Type and Low ADV Type) * Supports Synchronous Burst Read and Synchronous Burst Write Operation * Synchronous Burst(Read/Write) Operation - Supports 4 word / 8 word / 16 word and Full Page(256 word) burst - Supports Linear Burst type & Interleave Burst type - Latency support : Latency 5 @ 66MHz(tCD 10ns) Latency 4 @ 54MHz(tCD 10ns) - Supports Burst Read Suspend in No Clock toggling - Supports Burst Write Data Masking by /UB & /LB pin control - Supports WAIT pin function for indicating data availability. * Max. Burst Clock Frequency : 66MHz * Package Type : 54 ball FBGA 6.0mm x 8.0mm
Table 1. PRODUCT FAMILY
Product Family Operating Temp. Vcc Range Current Consumption Clock Async. Standby(Max) Standby(Max) Operating Freq.(Max) Speed(tAA) (ISB1, <40C) (ISB1, <85C) (ICC2, ICC3, Max.) 66MHz 70ns 120A 180A 40mA
K1B6416B6C-I
Industrial(-40~85C)
1.7~2.0V
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
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K1B6416B6C
Fig.1 PIN DESCRIPTION
1 2 3 4 5 6
UtRAM
Table 2. PIN DESCRIPTION
Name CLK Function Clock Input Address Input Valid Mode Register set Chip Select Output Enable Input Write Enable Input Address Inputs Name Function
I/O0~I/O15 Data Inputs/Outputs VCC/VCCQ Power Supply Vss/VSSQ UB LB WAIT NC Ground Upper Byte(I/O8~15) Lower Byte(I/O0~7) Data Availability Not Connected
A
LB
OE
A0
A1
A2
MRS
ADV MRS
B
I/O8
UB
A3
A4
CS
I/O0
CS
C I/O9 I/O10 A5 A6 I/O1 I/O2
OE WE
D
VSSQ
I/O11
A17
A7
I/O3
Vcc
A0~A21
E
VCCQ
I/O12
A21
A16
I/O4
Vss
F
I/O14
I/O13
A14
A15
I/O5
I/O6
G
I/O15
A19
A12
A13
WE
I/O7
H
A18
A8
A9
A10
A11
A20
J
WAIT
CLK
ADV
NC
NC
NC
54-FBGA: Top View(Ball Down)
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K1B6416B6C
CONTENTS
Revision History Features and General Description Pin Description Power Up Sequence Functional Description Mode Register Setting Operation Mode Register Setting Timing Asynchronous Operation Asynchronous 4 Page Read Operation Asynchronous Write Operation Asynchronous Write Operation in Synchronous Mode Synchronous Burst Operation Synchronous Burst Read Operation Synchronous Burst Write Operation Synchronous Burst Operation Terminology Clock Latency Count Burst Length Burst Stop WAIT Control Burst Type Low Power Features Internal TCSR Driver Strength Optimization Partial Array Refresh(PAR) Mode Product List Absolute Maximum Ratings Recommended DC Operating Conditions Capacitance DC and Operating Characteristics Asynchronous AC Characteristics Asynchronous Timing Waveforms Synchronous AC Characteristics Synchronous Timing Waveforms Transition Timing Waveforms Package Dimension
UtRAM
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K1B6416B6C
LIST of TABLES
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Product Family Pin Description Asynchronous 4 Page Read & Asynchronous Write Mode Truth Table Synchronous Burst Read & Asynchronous Write Mode Truth Table Synchronous Burst Read & Synchronous Burst Write Mode Truth Table Mode Register Setting according to Field of Function Mode Register Set MRS AC Characteristics Latency Count Support Number of Clocks for 1st Data Burst Sequence PAR Mode Characteristics Product List Absolute Maximum Ratings Recommended DC Operating Conditions Capacitance DC and Operating Characteristics Asynchronous AC Characteristics Asynchronous Read AC Characteristics Asynchronous Page Read AC Characteristics Asynchronous Write AC Characteristics(WE Controlled) Asynchronous Write AC Characteristics(UB & LB Controlled) Asynch. Write in Synch. Mode AC Characteristics(Address Latch Type, WE Controlled) Asynch. Write in Synch. Mode AC Characteristics(Address Latch Type, UB & LB Controlled) Asynch. Write in Synch. Mode AC Characteristics(Low ADV Type, WE Controlled) Asynch. Write in Synch. Mode AC Characteristics(Low ADV Type, UB & LB Controlled) Asynch. Write in Synch. Mode AC Characteristics(Low ADV Type Multiple Write, WE Controlled) Synchronous AC Characteristics Burst Operation AC Characteristics Burst Read AC Characteristics(CS Toggling Consecutive Burst) Burst Read AC Characteristics(CS Low Holding Consecutive Burst) Burst Read AC Characteristics(Last Data Sustaining) Burst Write AC Characteristics(CS Toggling Consecutive Burst) Burst Write AC Characteristics(CS Low Holding Consecutive Burst) Burst Read Stop AC Characteristics Burst Write Stop AC Characteristics Burst Read Suspend AC Characteristics Burst Read to Asynch. Write(Address Latch Type) AC Characteristics Burst Read to Asynch. Write(Low ADV Type) AC Characteristics Asynch. Write(Address Latch Type) to Burst Read AC Characteristics Asynch. Write(Low ADV Type) to Burst Read AC Characteristics Burst Read to Burst Write AC Characteristics Burst Write to Burst Read AC Characteristics
UtRAM
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LIST of FIGURES
Figure 1. Pin Description Figure 2. Functional Block Diagram Figure 3. Power Up Timing Figure 4. Standby Mode State Machine Figure 5. Mode Register Setting Timing Figure 6. Asynchronous 4-Page Read Figure 7. Asynchronous Write Figure 8. Synchronous Burst Read Figure 9. Synchronous Burst Write Figure 10. Latency Configuration(Read) Figure 11. WAIT Control and Read/Write Latency Control Figure 13. PAR Mode Execution and Exit Figure 14. AC Output Load Circuit(Asynchronous) Figure 15. Timing Waveform of Asynchronous Read Cycle Figure 16. Timing Waveform of Page Read Cycle Figure 17. Timing Waveform of Write Cycle(Asynchronous, WE Controlled) Figure 18. Timing Waveform of Write Cycle(Asynchronous, UB & LB Controlled) Figure 19. Timing Waveform of Write Cycle(Asynchronous, Address Latch Type, WE Controlled) Figure 20. Timing Waveform of Write Cycle(Asynchronous, Address Latch Type, UB & LB Controlled) Figure 21. Timing Waveform of Write Cycle(Asynchronous, Low ADV Type, WE Controlled) Figure 22. Timing Waveform of Write Cycle(Asynchronous, Low ADV Type, UB & LB Controlled) Figure 23. Timing Waveform of Multiple Write Cycle(Asynchronous, Low ADV Type, WE Controlled ) Figure 24. AC Output Load Circuit(Synchronous) Figure 25. Timing Waveform of Basic Burst Operation Figure 26. Timing Waveform of Burst Read Cycle(CS Toggling Consecutive Burst Read) Figure 27. Timing Waveform of Burst Read Cycle(CS Low Holding Consecutive Burst Read) Figure 28. Timing Waveform of Burst Read Cycle(Last Data Sustaining) Figure 29. Timing Waveform of Burst Write Cycle(CS Toggling Consecutive Burst Write) Figure 30. Timing Waveform of Burst Write Cycle(CS Low Holding Consecutive Burst Write) Figure 31. Timing Waveform of Burst Read Stop by CS Figure 32. Timing Waveform of Burst Write Stop by CS Figure 33. Timing Waveform of Burst Read Suspend Cycle Figure 34. Synch. Burst Read to Asynch. Write(Address Latch Type) Timing Waveform Figure 35. Synch. Burst Read to Asynch. Write(Low ADV Type) Timing Waveform Figure 36. Asynch. Write(Address Latch Type) to Synch. Burst Read Timing Waveform Figure 37. Asynch. Write(Low ADV Type) to Synch. Burst Read Timing Waveform Figure 38. Synch. Burst Read to Synch. Burst Write Timing Waveform Figure 39. Synch. Burst Write to Synch. Burst Read Timing Waveform
UtRAM
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Fig.2 FUNCTIONAL BLOCK DIAGRAM
UtRAM
CLK generator
Precharge circuit.
Vcc Vss
Row Addresses
Row select
Memory array
I/O0~I/O7
Data controller Data controller Data controller
I/O Circuit Column select
I/O8~I/O15
Column Addresses
CLK ADV MRS CS OE WE UB LB WAIT
Control Logic
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POWER UP SEQUENCE
UtRAM
After applying VCC upto minimum operating voltage(1.7V), drive CS High first and then drive MRS High. Then the device gets into the Power Up mode. Wait for minimum 200s to get into the normal operation mode. During the Power Up mode, the standby current can not be guaranteed. To get the stable standby current level, at least one cycle of active operation should be implemented regardless of wait time duration. To get the appropriate device operation, be sure to keep the following power up sequence. 1. Apply power. 2. Maintain stable power(Vcc min.=1.7V) for a minimum 200s with CS and MRS high.
Fig.3 POWER UP TIMING
200s VCC(Min) VCC Min. 0ns MRS
~
Min. 200s

CS
Min. 0ns
Power Up Mode
(Note)
Normal Operation
1. After VCC reaches VCC(Min.), wait 200s with CS and MRS high. Then the device gets into the normal operation.
Fig.4 STANDBY MODE STATE MACHINES
CS=VIH MRS=VIH Power On Initial State (Wait 200s) CS=UB=LB=VIL, WE=VIL, MRS=VIL MRS Setting CS=VIL, UB or LB=VIL MRS=VIH Active
CS=VIH Standby Mode MRS=VIH MRS=VIL PAR Mode
MRS Setting CS=VIL, WE=VIL, MRS=VIL
Default mode after power up is Asynchronous mode(4 Page Read and Asynchronous Write). But this default mode is not 100% guaranteed so MRS setting sequence is highly recommended after power up. For entry to PAR mode, drive MRS pin into VIL for over 0.5s(suspend period) during standby mode after MRS setting has been completed(A4=1, A3=0). If MRS pin is driven into VIH during PAR mode, the device gets back to the standby mode without wake up sequence.
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FUNCTIONAL DESCRIPTION Table 3. ASYNCHRONOUS 4 PAGE READ & ASYNCHRONOUS WRITE MODE(A15/A14=0/0)
CS H H L L L L L L L L L MRS H L H H H H H H H H L OE X
1)
UtRAM
WE X
1)
LB X
1)
UB X
1)
I/O0~7 High-Z High-Z High-Z High-Z Dout High-Z Dout Din High-Z Din High-Z
I/O8~15 High-Z High-Z High-Z High-Z High-Z Dout Dout High-Z Din Din High-Z
Mode Deselected Deselected Output Disabled Output Disabled Lower Byte Read Upper Byte Read Word Read Lower Byte Write Upper Byte Write Word Write Mode Register Set
Power Standby PAR Active Active Active Active Active Active Active Active Active
X1) H X1) L L L H H H H
X1) H X1) H H H L L L L
X1) X
1)
X1) X
1)
H L H L L H L L
H H L L H L L L
1. X must be low or high state. 2. In asynchronous mode, Clock and ADV are ignored. 3. /WAIT pin is High-Z in Asynchronous mode.
Table 4. SYNCHRONOUS BURST READ & ASYNCHRONOUS WRITE MODE(A15/A14=0/1)
CS H H L L L L L L L L L L MRS H L H H H H H H H H H L OE X1) X1) H X1) X1) L L L H H H H WE X1) X1) H X1) H H H H L L L L LB X1) X1) X1) H X1) L H L L H L L UB X1) X1) X1) H X1) H L L H L L L I/O0~7 High-Z High-Z High-Z High-Z High-Z Dout High-Z Dout Din High-Z Din High-Z I/O8~15 High-Z High-Z High-Z High-Z High-Z High-Z Dout Dout High-Z Din Din High-Z X
2)
CLK X2) X2) X2) X2)
ADV X2) X2) H H
Mode Deselected Deselected Output Disabled Output Disabled Read Command
Power Standby PAR Active Active Active Active Active Active Active Active Active Active
H H H or or or or
Lower Byte Read Upper Byte Read Word Read Lower Byte Write Upper Byte Write Word Write Mode Register Set
X2) X
2)
X2)
1. X must be low or high state. 2. X means "Don't care"(can be low, high or toggling). 3. /WAIT is device output signal so does not have any affect to the mode definition. Please refer to each timing diagram for /WAIT pin function.
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Table 5. SYNCHRONOUS BURST READ & SYNCHRONOUS BURST WRITE MODE(A15/A14=1/0)
CS H H L L L L L L L L L L L MRS H L H H H H H H H H H H L OE X
1)
UtRAM
WE X
1)
LB X
1)
UB X
1)
I/O0~7 High-Z High-Z High-Z High-Z High-Z Dout High-Z Dout High-Z Din High-Z Din High-Z
I/O8~15 High-Z High-Z High-Z High-Z High-Z High-Z Dout Dout High-Z High-Z Din Din High-Z
CLK X
2)
ADV X
2)
Mode Deselected Deselected Output Disabled Output Disabled Read Command
Power Standby PAR Active Active Active Active Active Active Active Active Active Active Active
X1) H X1) X
1)
X1) H X1) H H H H L or X
1)
X1) X
1)
X1) X
1)
X2) X
2)
X2) H H
H X
1)
H X
1)
X2)
L L L X
1)
L H L X
1)
H L L X
1)
H H H
Lower Byte Read Upper Byte Read Word Read Write Command
H H H H
L H L L
H L L L
H H H
Lower Byte Write Upper Byte Write Word Write Mode Register Set
X1) X1) L or
1. X must be low or high state. 2. X means "Don't care"(can be low, high or toggling). 3. /WAIT is device output signal so does not have any affect to the mode definition. Please refer to each timing diagram for /WAIT pin function. 4. The last data written in the previous Asynchronous write mode is not valid. To make the lastly written data valid, then implement at least one dummy write cycle before change mode into synchronous burst read and synchronous burst write mode. 5. The data written in Synchronous burst write operation can be corrupted by the next Asynchronous write operation. So the transition from Synchronous burst write operation to Asynchronous write operation is prohibited.
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MODE REGISTER SETTING OPERATION
UtRAM
The device has several modes : Asynchronous Page Read mode, Asynchronous Write mode, Synchronous Burst Read mode, Synchronous Burst Write mode, Standby mode and Partial Array Refresh(PAR) mode. Partial Array Refresh(PAR) mode is defined through Mode Register Set(MRS) option. Mode Register Set(MRS) option also defines Burst Length, Burst Type, Wait Polarity and Latency Count at Synchronous Burst Read/Write mode.
Mode Register Set (MRS)
The mode register stores the data for controlling the various operation modes of UtRAM. It programs Partial Array Refresh(PAR), Burst Length, Burst Type, Latency Count and various vendor specific options to make UtRAM useful for a variety of different applications. The default values of mode register are defined, therefore when the reserved address is input, the device runs at default modes. The mode register is written by driving CS, ADV, WE, UB, LB and MRS to VIL and driving OE to VIH during valid address. The mode register is divided into various fields depending on the fields of functions. The Partial Array Refresh(PAR) field uses A0~A4, Burst Length field uses A5~A7, Burst Type uses A8, Latency Count uses A9~A11, Wait Polarity uses A13, Operation Mode uses A14~A15 and Driver Strength uses A16~A17. Refer to the Table below for detailed Mode Register Setting. A18~A21 addresses are "Don't care" in Mode Register Setting. Table 6. Mode Register Setting according to field of function Address Function A17~A16 DS A15~A14 MS A13 WP A12 RFU A11~A9 Latency A8 BT A7~A5 BL A4~A3 PAR A2 PARA A1~A0 PARS
NOTE : DS(Driver Strength), MS(Mode Select), WP(Wait Polarity), Latency(Latency Count), BT(Burst Type), BL(Burst Length), PAR(Partial Array Refresh), PARA(Partial Array Refresh Array), PARS(Partial Array Refresh Size), RFU(Reserved for Future Use) Table 7. Mode Register Set
Driver Strength A17 0 0 1 A16 0 1 0 WAIT Polarity A13 0 1 WP Low Enable High Enable A12 0 1 DS Full Drive 1/2 Drive 1/4 Drive RFU RFU Must A11 0 0 0 0 Partial Array Refresh A4 1 1 A3 0 1 PAR PAR Enable PAR Disable A2 0 1 PAR Array PARA Bottom Array Top Array A1 0 0 1 1 A15 0 0 1 A14 0 1 0 Mode Select MS* Async. 4 Page Read / Async. Write Sync. Burst Read / Async. Write Sync. Burst Read / Sync. Burst Write Latency Count A10 0 0 1 1 A9 0 1 0 1 PAR Size A0 0 1 0 1 PARS Full Array 3/4 Array 1/2 Array 1/4 Array Latency 3 4 5 6 A8 0 1 Burst Type BT Linear Interleave A7 0 0 1 1 A6 1 1 0 1 Burst Length A5 0 1 0 1 BL 4 word 8 word 16 word Full(256 word)
NOTE : The address bits other than those listed in the table above are reserved. For example, Burst Length address bits(A7:A6:A5) have 4 sets of reserved bits like 0:0:0, 0:0:1, 1:0:1 and 1:1:0. If the reserved address bits are input, then the mode will be set into the default mode. Each field has its own default mode and these default modes are written in blue-bold in the table above. But this default mode is not 100% guaranteed so MRS setting sequence is highly recommended after power up. A12 is a reserved bit for future use. A12 must be set as "0". Not all the mode settings are tested. Per the mode settings to be tested, please contact Samsung Product Planning team. 256 word Full page burst mode needs to meet tBC(Burst Cycle time) parameter as max. 2500ns. * The last data written in the previous Asynchronous write mode is not valid. To make the lastly written data valid, then implement at least one dummy write cycle before change mode into synchronous burst read and synchronous burst write mode. * The data written in Synchronous burst write operation can be corrupted by the next Asynchronous write operation. So the transition from Synchronous burst write operation to Asynchronous write operation is prohibited.
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MRS pin Control Type Mode Register Setting Timing
UtRAM
In this device(K1B6416B6C), MRS pin is used for two purposes. One is to get into the mode register setting and the other one is to execute Partial Array Refresh mode. To get into the Mode Register Setting, the system must drive MRS pin to VIL and immediately(within 0.5s) issue a write command(drive CS, ADV, UB, LB and WE to VIL and drive OE to VIH during valid address). If the subsequent write command(WE signal input) is not issued within 0.5s, then the device might get into the PAR mode.
Fig.5 MODE REGISTER SETTING TIMING(OE=VIH)
0
CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
ADV
tWC
Address
tCW
CS
tAW tBW
UB, LB
tWP
WE
tAS tMW tWU
MRS
Register Update Complete Register Write Start
(MRS SETTING TIMING) 1. Clock input is ignored.
Register Write Complete
Table 8. MRS AC CHARACTERISTICS (VCC=1.7~2.0V, TA=-40 to 85C, Maximum Main Clock Frequency=66MHz)
Parameter List MRS Enable to Register Write Start End of Write to MRS Disable Symbol Min MRS tMW tWU 0 0 Speed Max 500 ns ns Units
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ASYNCHRONOUS OPERATION
Asynchronous 4 Page Read Operation
Asynchronous normal read operation starts when CS, OE and UB or LB are driven to VIL under the valid address without toggling page addresses(A0, A1). If the page addresses(A0, A1) are toggled under the other valid address, the first data will be out with the normal read cycle time(tRC) and the second, the third and the fourth data will be out with the page cycle time(tPC). (MRS and WE should be driven to VIH during the asynchronous (page) read operation) Clock, ADV, WAIT signals are ignored during the asynchronous (page) read operation.
UtRAM
SYNCHRONOUS BURST OPERATION
Burst mode operations enable the system to get high performance read and write operation. The address to be accessed is latched on the rising edge of clock or ADV(whichever occurs first). CS should be setup before the address latch. During this first clock rising edge, WE indicates whether the operation is going to be a Read(WE High) or a Write(WE Low). For the optimized Burst Mode to each system, the system should determine how many clock cycles are required for the first data of each burst access(Latency Count), how many words the device outputs at an access(Burst Length) and which type of burst operation(Burst Type : Linear or Interleave) is needed. The Wait Polarity should also be determined.(See Table "Mode Register Set")
Asynchronous Write Operation
Asynchronous write operation starts when CS, WE and UB or LB are driven to VIL under the valid address.(MRS and OE should be driven to VIH during the asynchronous write operation.) Clock, ADV, WAIT signals are ignored during the asynchronous (page) read operation.
Synchronous Burst Read Operation
The Synchronous Burst Read command is implemented when the clock rising is detected during the ADV low pulse. ADV and CS should be set up before the clock rising. During Read command, WE should be held in VIH. The multiple clock risings(during low ADV period) are allowed but the burst operation starts from the first clock rising. The first data will be out with Latency count and tCD.
Asynchronous Write Operation in Synchronous Mode
A write operation starts when CS, WE and UB or LB are driven to VIL under the valid address. Clock input does not have any affect to the write operation(MRS and OE should be driven to VIH during write operation. ADV can be either toggling for address latch or held in VIL). Clock, ADV, WAIT signals are ignored during the asynchronous (page) read operation. Fig.6 ASYNCHRONOUS 4-PAGE READ
A21~A2
Synchronous Burst Write Operation
The Synchronous Burst Write command is implemented when the clock rising is detected during the ADV and WE low pulse. ADV, WE and CS should be set up before the clock rising. The multiple clock risings(during low ADV period) are allowed but the burst operation starts from the first clock rising. The first data will be written in the Latency clock with tDS. Fig.8 SYNCHRONOUS BURST READ(Latency 5, BL 4, WP : Low Enable)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
CLK ADV
A1~A0 Addr. CS CS UB, LB OE OE Data out Data out WAIT
UB, LB
Fig.7 ASYNCHRONOUS WRITE
Address
Fig.9 SYNCHRONOUS BURST WRITE(Latency 5, BL 4, WP : Low Enable)
0 1 2 3 4 5 6 7 8 9 10 11 12 13
CLK ADV
CS Addr. UB, LB CS UB, LB WE Data in
High-Z
WE
Data in Data out
High-Z High-Z
WAIT
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SYNCHRONOUS BURST OPERATION TERMINOLOGY Clock(CLK)
UtRAM
The clock input is used as the reference for synchronous burst read and write operation of UtRAM. The synchronous burst read and write operation is synchronized to the rising edge of the clock. The clock transitions must swing between VIL and VIH.
Latency Count
The Latency Count configuration tells the device how many clocks must elapse from the burst command before the first data should be available on its data pins. This value depends on the input clock frequency. The supported Latency Count is as follows. Table 9. Latency Count support : 3, 4, 5 Clock Frequency Latency Count Table 10. Number of Clocks for 1st Data Set Latency # of Clocks for 1st data(Read) # of Clocks for 1st data(Write) Fig.10 Latency Configuration(Read)
T
Upto 66MHz 5
Upto 54MHz 4
Upto 40MHz 3
Latency 3 4 2
Latency 4 5 3
Latency 5 6 4
Clock
ADV
Address Latency 3 Data out Latency 4 Data out Latency 5 Data out Latency 6 Data out
DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9
NOTE : The first data will always keep the Latency. From the second data, some period of wait time might be caused by WAIT pin.
Burst Length
Burst Length identifies how many data the device outputs at an access. The device supports 4 word, 8 word, 16 word and 256 word burst read or write. 256 word Full page burst mode needs to meet tBC(Burst Cycle time) parameter as max. 2500ns. The first data will be out with the set Latency + tCD. From the second data, the data will be out with tCD from each clock.
Burst Stop
Burst stop is used when the system wants to stop burst operation on special purpose. If driving CS to VIH during the burst read operation, then the burst operation will be stopped. During the burst read operation, the new burst operation can not be issued. The new burst operation can be issued only after the previous burst operation is finished. The burst stop feature is very useful because it enables the user to utilize the un-supported burst length such as 1 burst or 2 burst which accounts for big portion in usage for the mobile handset application environment.
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SYNCHRONOUS BURST OPERATION TERMINOLOGY WAIT Control(WAIT)
UtRAM
The WAIT signal is the device's output signal which indicates to the host system when the device's data-out or data-in is valid. To be compatible with the Flash interfaces of various microprocessor types, the WAIT polarity(WP) can be configured. The polarity can be programmed to be either low enable or high enable. For the timing of WAIT signal, the WAIT signal should be set active one clock prior to the data regardless of Read or Write cycle.
Fig.11 WAIT Control and Read/Write Latency Control(LATENCY : 5, Burst Length : 4, WP : Low Enable)
0
CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
ADV Latency 5
CS Read Data out WAIT Write Data in WAIT
DQ0
DQ1
DQ2
DQ3
High-Z
Latency 5 D0 D1 D2 D3
High-Z
Burst Type
The device supports Linear type burst sequence and Interleave type burst sequence. Linear type burst sequentially increments the burst address from the starting address. The detailed Linear and Interleave type burst address sequence is shown in burst sequence table in next page.
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Table 11. Burst Sequence
Burst Address Sequence(Decimal) Start Addr. Wrap1) 4 word Burst Linear 0 1 2 3 4 5 6 7 ~ 14 15 ~ 255 1. Wrap : Burst Address wraps within word boundary and ends after fulfilled the burst length. 2. 256 word Full page burst mode needs to meet tBC(Burst Cycle time) parameter as max. 2500ns. 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 Interleave 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 8 word Burst Linear 0-1-...-5-6-7 1-2-...-6-7-0 2-3-...-7-0-1 3-4-...-0-1-2 4-5-...-1-2-3 5-6-...-2-3-4 6-7-...-3-4-5 7-0-...-4-5-6 Interleave 0-1-2-...-6-7 1-0-3-...-7-6 2-3-0-...-4-5 3-2-1-...-5-4 4-5-6-...-2-3 5-4-7-...-3-2 6-7-4-...-0-1 7-6-5-...-1-0 16 word Burst Linear 0-1-2-...-14-15 1-2-3-...-15-0 2-3-4-...-0-1 3-4-5-...-1-2 4-5-6-...-2-3 5-6-7-...-3-4 6-7-8-...-4-5 7-8-9-...-5-6 ~ 14-15-0-...-12-13 15-0-1-...-13-14 Interleave 0-1-2-3-4...14-15 1-0-3-2-5...15-14 2-3-0-1-6...12-13 3-2-1-0-7...13-12 4-5-6-7-0...10-11 5-4-7-6-1...11-10 6-7-4-5-2...8-9 7-6-5-4-3...9-8 ~ 14-15-12-...-0-1 15-14-13-...-1-0
UtRAM
Full Page(256 word) Linear 0-1-2-...-254-255 1-2-3-...-255-0 2-3-4-...-255-0-1 3-4-5-...-255-0-1-2 4-5-6-...-255-0-1-2-3 5-6-7-...-255-...-3-4 6-7-8-...-255-...-4-5 7-8-9-...-255-...-5-6 ~ 14-15-...-255-...-12-13 15-16-...-255-...-13-14 ~ 255-0-1-...-253-254
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LOW POWER FEATURES
Partial Array Refresh(PAR) mode
The PAR mode enables the user to specify the active memory array size. UtRAM consists of 4 blocks and user can select 1 block, 2 blocks, 3 blocks or all blocks as active memory array through Mode Register Setting. The active memory array is periodically refreshed whereas the disabled array is not going to be refreshed and so the previously stored data will get lost. Even though PAR mode is enabled through the Mode Register Setting, PAR mode execution by MRS pin is still needed. The normal operation can be executed even in refresh-disabled array as long as MRS pin is not driven to low for over 0.5s. Driving MRS pin to high makes the device to get back to the normal operation mode from PAR executed mode, Refer to Fig.13 and Table 12 for PAR operation and PAR address mapping. Fig.13 PAR MODE EXECUTION and EXIT
0.5s MRS
UtRAM
Driver Strength Optimization
The optimization of output driver strength is possible through the mode register setting to adjust for the different data loadings. Through this driver strength optimization, the device can minimize the noise generated on the data bus during read operation. The device supports full drive, 1/2 drive and 1/4 drive.
Internal TCSR
The internal Temperature Compensated Self Refresh(TCSR) feature is a very useful tool for reducing standby current in room temperature(below 40C). DRAM cell has weak refresh characteristics in higher temperature. So high temperature requires more refresh cycles, which lead to standby current increase. Without internal TCSR, the refresh cycle should be set as worst condition so as to cover high temperature(85C) refresh characteristics. But with internal TCSR, the refresh cycle below 40C can be optimized, so the standby current in room temperature can be highly reduced. This feature is really beneficial to mobile phone because most of mobile phones are used at below 40C in the phone standby mode.
Normal Operation MODE
Suspend
PAR mode
Normal Operation
CS
Table 12. PAR MODE CHARACTERISTIC
Power Mode Standby(Full Array) Partial Refresh(3/4 Block) Partial Refresh(1/2 Block) Partial Refresh(1/4 Block) Address (Bottom Array)2) 000000h ~ 3FFFFFh 000000h ~ 2FFFFFh 000000h ~ 1FFFFFh 000000h ~ 0FFFFFh Address (Top Array)2) 000000h ~ 3FFFFFh 100000h ~ 3FFFFFh 200000h ~ 3FFFFFh 300000h ~ 3FFFFFh Memory Standby3) Standby3) Cell Data (ISB1, <40C) (ISB1, <85C) Valid1) Valid1) Valid1) Valid
1)
Wait Time(s) 0 0 0 0
120A 120A 115A 115A
180A 180A 165A 165A
1. Only the data in the refreshed block are valid 2. PAR Array can be selected through Mode Register Set(See Page 11) 3. Standby mode is supposed to be set up after at least one active operation.after power up. ISB1 is measured after 60ms from the time when standby mode is set up.
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Table 13. PRODUCT LIST
Industrial Temperature Products(-40~85C) Part Name K1B6416B6C Function 1.8V, 70ns, 66MHz
UtRAM
Table 14. ABSOLUTE MAXIMUM RATINGS1)
Item Voltage on any pin relative to Vss Power supply voltage relative to Vss Power Dissipation Storage temperature Operating Temperature Symbol VIN, VOUT VCC PD TSTG TA Ratings -0.2 to VCC+0.3V -0.2 to 2.5V 1.0 -65 to 150 -40 to 85 Unit V V W C C
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to be used under recommended operating condition. Exposure to absolute maximum rating conditions longer than 1 second may affect reliability.
Table 15. RECOMMENDED DC OPERATING CONDITIONS1)
Item Power supply voltage Ground Input high voltage Input low voltage
1. TA=-40 to 85C, otherwise specified. 2. Overshoot: VCC+1.0V in case of pulse width 20ns. 3. Undershoot: -1.0V in case of pulse width 20ns. 4. Overshoot and undershoot are sampled, not 100% tested.
Symbol VCC Vss VIH VIL
Min 1.7 0 0.8 x VCC -0.2
3)
Typ 1.85 0 -
Max 2.0 0 VCC+0.22) 0.4
Unit V V V V
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Table 16. CAPACITANCE1)(f=1MHz, TA=25C)
Item Input capacitance Input/Output capacitance
1. Capacitance is sampled, not 100% tested.
UtRAM
Symbol CIN CIO
Test Condition VIN=0V VIO=0V
Min -
Max 8 10
Unit pF pF
Table 17. DC AND OPERATING CHARACTERISTICS
Item Input Leakage Current Output Leakage Current Average Operating Current(Async) Average Operating Current(Sync) Output Low Voltage Output High Voltage Standby Current(CMOS)
Symbol
Test Conditions VIN=Vss to VCCQ CS=VIH, MRS=VIH, OE=VIH or WE=VIL, VIO=Vss to VCCQ Cycle time=tRC+3tPC, IIO=0mA, 100% duty, CS=VIL, MRS=VIH, VIN=VIL or VIH Burst Length 4, Latency 5, 66MHz, IIO=0mA, Address transition 1 time, CS=VIL, MRS=VIH, VIN=VIL or VIH IOL=0.1mA IOH=-0.1mA CSVCCQ-0.2V, MRSVCCQ-0.2V, Other inputs=Vss to VCCQ < 40C < 85C 3/4 Block < 40C 1/2 Block 1/4 Block 3/4 Block < 85C 1/2 Block 1/4 Block
Min -1 -1 1.4 -
Typ -
Max 1 1 40 40 0.2 120 180 120 115 115 180 165 165
Unit A A mA mA V V A A A
ILI ILO ICC2 ICC3 VOL VOH ISB12)
Partial Refresh Current
ISBP1)
MRS0.2V, CSVCCQ-0.2V Other inputs=Vss to VCCQ
A
1. Full Array Partial Refresh Current(ISBP) is same as Standby Current(ISB1). 2. Standby mode is supposed to be set up after at least one active operation.after power up. ISB1 is measured after 60ms from the time when standby mode is set up.
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AC OPERATING CONDITIONS
TEST CONDITIONS(Test Load and Test Input/Output Reference)
Input pulse level: 0.2 to VCC-0.2V Input rising and falling time: 3ns Input and output reference voltage: 0.5 x VCC Output load: CL=30pF
Figure 14. AC Output Load Circuit
UtRAM
Vtt=0.5 x VCC
50 Dout Z0=50 30pF
Table 18. ASYNCHRONOUS AC CHARACTERISTICS (VCC=1.7~2.0V, TA=-40 to 85C)
Parameter List Common CS High Pulse Width Read Cycle Time Page Read Cycle Time Address Access Time Page Access Time Chip Select to Output Output Enable to Valid Output Async. (Page) Read UB, LB Access Time Chip Select to Low-Z Output UB, LB Enable to Low-Z Output Output Enable to Low-Z Output Chip Disable to High-Z Output UB, LB Disable to High-Z Output Output Disable to High-Z Output Output Hold Write Cycle Time Chip Select to End of Write ADV Minimum Low Pulse Width Address Set-up Time to Beginning of Write Address Set-up Time to ADV Falling Address Hold Time from ADV Rising Async. Write CS Setup Time to ADV Rising Address Valid to End of Write UB, LB Valid to End of Write Write Pulse Width WE High Pulse Width Write Recovery Time WE Low to Read Latency Data to Write Time Overlap Data Hold from Write Time
1. tWP(min)=70ns for continuous write operation over 50 times.
Symbol Min tCSHP(A) tRC tPC tAA tPA tCO tOE tBA tLZ tBLZ tOLZ tCHZ tBHZ tOHZ tOH tWC tCW tADV tAS tAS(A) tAH(A) tCSS(A) tAW tBW tWP tWHP tWR tWLRL tDW tDH 10 70 25 10 5 5 0 0 0 3 70 60 7 0 0 7 10 60 60 551) 5 ns 0 1 30 0
Speed Max 70 20 70 35 35 12 12 12 Latency-1 clock -
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns clock ns ns
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ASYNCHRONOUS READ TIMING WAVEFORM
Fig.15 TIMING WAVEFORM OF ASYNCHRONOUS READ CYCLE (MRS=VIH, WE=VIH, WAIT=High-Z)
tRC
Address
UtRAM
tCSHP(A)
CS
tAA tCO
tOH
tCHZ tBA
UB, LB
tBHZ tOE
OE
Data out
High-Z
tOLZ tBLZ tLZ Data Valid
tOHZ
(ASYNCHRONOUS READ CYCLE) 1. tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tCHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. 3. In asynchronous read cycle, Clock, ADV and WAIT signals are ignored.
Table 19. ASYNCHRONOUS READ AC CHARACTERISTICS
Symbol Min tRC tAA tCO tBA tOE tOH tCSHP(A) 70 3 10 Speed Max 70 70 35 35 ns ns ns ns ns ns ns tOLZ tBLZ tLZ tCHZ tBHZ tOHZ Units Symbol Min 5 5 10 0 0 0 Speed Max 12 12 12 ns ns ns ns ns ns Units
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ASYNCHRONOUS READ TIMING WAVEFORM
Fig.16 TIMING WAVEFORM OF PAGE READ CYCLE(MRS=VIH, WE=VIH, WAIT=High-Z)
tRC A21~A2 tAA A1~A0
Valid Address Valid Address Valid Address Valid Address Valid Address
UtRAM
tOH
tPC tCO CS tBA UB, LB tBHZ tOE OE tLZ High Z tOLZ tBLZ tPA
Data Valid Data Valid Data Valid Data Valid
tCHZ tOHZ
Data out
(ASYNCHRONOUS 4 PAGE READ CYCLE) 1. tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tCHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. 3. In asynchronous 4 page read cycle, Clock, ADV and WAIT signals are ignored.
Table 20. ASYNCHRONOUS PAGE READ AC CHARACTERISTICS
Symbol Min tRC tAA tPC tPA tCO tBA tOE 70 25 Speed Max 70 20 70 35 35 ns ns ns ns ns ns ns tOH tOLZ tBLZ tLZ tCHZ tBHZ tOHZ Units Symbol Min 3 5 5 10 0 0 0 Speed Max 12 12 12 ns ns ns ns ns ns ns Units
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ASYNCHRONOUS WRITE TIMING WAVEFORM
Fig.17 TIMING WAVEFORM OF WRITE CYCLE(1)(MRS=VIH, OE=VIH, WAIT=High-Z, WE Controlled)
tWC Address tAW tCW CS tBW UB, LB tWP WE tAS tDH tDW Data Valid tWHP tAS tDH tDW Data Valid tWP tBW tWR tCSHP(A) tAW tCW tWR tWC
UtRAM
Data in
Data out
High-Z
High-Z
(ASYNCHRONOUS WRITE CYCLE - WE Controlled) 1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition when CS goes high or WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the CS going low to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS or WE going high. 5. In asynchronous write cycle, Clock, ADV and WAIT signals are ignored. 6. Condition for continuous write operation over 50 times : tWP(min)=70ns
Table 21. ASYNCHRONOUS WRITE AC CHARACTERISTICS(WE Controlled)
Symbol Min tWC tCW tAW tBW tWP 70 60 60 60 55
1)
Speed Max -
Units ns ns ns ns ns
Symbol Min tAS tWR tDW tDH tCSHP(A) 0 0 30 0 10
Speed Max -
Units ns ns ns ns ns
1. tWP(min)=70ns for continuous write operation over 50 times.
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ASYNCHRONOUS WRITE TIMING WAVEFORM
Fig.18 TIMING WAVEFORM OF WRITE CYCLE(2)(MRS=VIH, OE=VIH, WAIT=High-Z, UB & LB Controlled)
tWC Address tCW CS tAW tBW UB, LB tAS tWP WE tDW Data in Data Valid tDH tWR
UtRAM
Data out
High-Z
High-Z
(ASYNCHRONOUS WRITE CYCLE - UB & LB Controlled) 1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition when CS goes high or WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the CS going low to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS or WE going high. 5. In asynchronous write cycle, Clock, ADV and WAIT signals are ignored.
Table 22. ASYNCHRONOUS WRITE AC CHARACTERISTICS(UB & LB Controlled)
Symbol Min tWC tCW tAW tBW tWP 70 60 60 60 55
1)
Speed Max -
Units ns ns ns ns ns
Symbol Min tAS tWR tDW tDH 0 0 30 0
Speed Max -
Units ns ns ns ns
1. tWP(min)=70ns for continuous write operation over 50 times.
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ASYNCHRONOUS WRITE TIMING WAVEFORM in SYNCHRONOUS MODE
UtRAM
Fig.19 TIMING WAVEFORM OF WRITE CYCLE(Address Latch Type)(MRS=VIH, OE=VIH, WAIT=High-Z, WE Controlled)
0 CLK tADV ADV Address CS UB, LB tWLRL WE tAS Data in Read Latency 5 Data out High-Z High-Z tDW Data Valid tDH tAS(A) tAH(A)
Valid
1
2
3
4
5
6
7
8
9
10
11
12
13
14
tCSS(A)
tCW tAW tBW tWP
(ADDRESS LATCH TYPE ASYNCHRONOUS WRITE CYCLE - WE Controlled) 1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB or LB for single byte operation or simultaneously asserting UB and LB for word operation. A write ends at the earliest transition when CS goes high or WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tAW is measured from the address valid to the end of write. In this address latch type write timing, tWC is same as tAW. 3. tCW is measured from the CS going low to the end of write. 4. tBW is measured from the UB and LB going low to the end of write. 5. Clock input does not have any affect to the write operation if the parameter tWLRL is met.
Table 23. ASYNCH. WRITE IN SYNCH. MODE AC CHARACTERISTICS(Address Latch Type, WE Controlled)
Symbol Min tADV tAS(A) tAH(A) tCSS(A) tCW tAW 7 0 7 10 60 60 Speed Max ns ns ns ns ns ns tBW tWP tWLRL tAS tDW tDH Units Symbol Min 60 55 1 0 30 0
1)
Speed Max -
Units ns ns clock ns ns ns
1. tWP(min)=70ns for continuous write operation over 50 times.
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ASYNCHRONOUS WRITE TIMING WAVEFORM in SYNCHRONOUS MODE
UtRAM
Fig.20 TIMING WAVEFORM OF WRITE CYCLE(Address Latch Type)(MRS=VIH, OE=VIH, WAIT=High-Z, UB & LB Controlled)
0 CLK tADV ADV Address CS tAS(A) tAH(A)
Valid
1
2
3
4
5
6
7
8
9
10
11
12
13
14
tCSS(A)
tCW tAW tBW
UB, LB tAS WE tWLRL
tWP tDW tDH
Data in Read Latency 5 Data out High-Z
Data Valid
High-Z
(ADDRESS LATCH TYPE ASYNCHRONOUS WRITE CYCLE - UB & LB Controlled) 1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB or LB for single byte operation or simultaneously asserting UB and LB for word operation. A write ends at the earliest transition when CS goes or and WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tAW is measured from the address valid to the end of write. In this address latch type write timing, tWC is same as tAW. 3. tCW is measured from the CS going low to the end of write. 4. tBW is measured from the UB and LB going low to the end of write. 5. Clock input does not have any affect to the write operation if the parameter tWLRL is met.
Table 24. ASYNCH. WRITE IN SYNCH. MODE AC CHARACTERISTICS(Address Latch Type, UB & LB Controlled)
Symbol Min tADV tAS(A) tAH(A) tCSS(A) tCW tAW 7 0 7 10 60 60 Speed Max ns ns ns ns ns ns tBW tWP tWLRL tAS tDW tDH Units Symbol Min 60 551) 1 0 30 0 Speed Max ns ns clock ns ns ns Units
1. tWP(min)=70ns for continuous write operation over 50 times.
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ASYNCHRONOUS WRITE TIMING WAVEFORM in SYNCHRONOUS MODE
UtRAM
Fig.21 TIMING WAVEFORM OF WRITE CYCLE(Low ADV Type)(MRS=VIH, OE=VIH, WAIT=High-Z, WE Controlled)
0 CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14
ADV tWC Address tCW CS UB, LB tWLRL WE Data in Read Latency 5 Data out High-Z High-Z tAS tDH tDW Data Valid tAW tBW tWP tWR
(LOW ADV TYPE WRITE CYCLE - WE Controlled) 1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition when CS goes high or WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the CS going low to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS or WE going high. 5. Clock input does not have any affect to the write operation if the parameter tWLRL is met.
Table 25. ASYNCH. WRITE IN SYNCH. MODE AC CHARACTERISTICS(Low ADV Type, WE Controlled)
Symbol Min tWC tCW tAW tBW tWP 70 60 60 60 551) Speed Max ns ns ns ns ns tWLRL tAS tWR tDW tDH Units Symbol Min 1 0 0 30 0 Speed Max clock ns ns ns ns Units
1. tWP(min)=70ns for continuous write operation over 50 times.
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ASYNCHRONOUS WRITE TIMING WAVEFORM in SYNCHRONOUS MODE
UtRAM
Fig.22 TIMING WAVEFORM OF WRITE CYCLE(Low ADV Type)(MRS=VIH, OE=VIH, WAIT=High-Z, UB & LB Controlled)
0 CLK ADV tWC Address tCW CS UB, LB WE tDH tDW Data Valid Read Latency 5 Data out High-Z High-Z tAW tBW tAS tWLRL tWP tWR 1 2 3 4 5 6 7 8 9 10 11 12 13 14
Data in
(LOW ADV TYPE WRITE CYCLE - UB & LB Controlled) 1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition when CS goes high or WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the CS going low to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS or WE going high. 5. Clock input does not have any affect to the write operation if the parameter tWLRL is met.
Table 26. ASYNCH. WRITE IN SYNCH. MODE AC CHARACTERISTICS(Low ADV Type, UB & LB Controlled)
Symbol Min tWC tCW tAW tBW tWP 70 60 60 60 551) Speed Max ns ns ns ns ns tWLRL tAS tWR tDW tDH Units Symbol Min 1 0 0 30 0 Speed Max clock ns ns ns ns Units
1. tWP(min)=70ns for continuous write operation over 50 times.
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ASYNCHRONOUS WRITE TIMING WAVEFORM in SYNCHRONOUS MODE
UtRAM
Fig.23 TIMING WAVEFORM OF MULTIPLE WRITE CYCLE(Low ADV Type)(MRS=VIH, OE=VIH, WAIT=High-Z, WE Controlled)
0 CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14
ADV tWC Address tAW tCW CS tBW UB, LB tWP WE tAS tDH tDW Data Valid tWHP tAS tDH tDW Data Valid tWP tBW tWR tAW tCW tWR tWC
Data in
Data out
High-Z
High-Z
(LOW ADV TYPE MULTIPLE WRITE CYCLE) 1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition when CS goes high or WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the CS going low to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS or WE going high. 5. Clock input does not have any affect to the asynchronous multiple write operation if tWHP is shorter than (Read Latency - 1) clock duration. 6. tWP(min)=70ns for continuous write operation over 50 times.
Table 27. ASYNCH. WRITE IN SYNCH. MODE AC CHARACTERISTICS(Low ADV Type Multiple Write, WE Controlled)
Symbol Min tWC tCW tAW tBW tWP 70 60 60 60 551) Speed Max ns ns ns ns ns tWHP tAS tWR tDW tDH Units Symbol Min 5ns 0 0 30 0 Speed Max Latency-1 clock ns ns ns ns Units
1. tWP(min)=70ns for continuous write operation over 50 times.
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AC OPERATING CONDITIONS
TEST CONDITIONS(Test Load and Test Input/Output Reference)
Input pulse level: 0.2 to VCC-0.2V Input rising and falling time: 3ns Input and output reference voltage: 0.5 x VCC Output load: CL=30pF
Figure 24. AC Output Load Circuit
UtRAM
Vtt=0.5 x VCC
50 Dout Z0=50 30pF
Table 28. SYNCHRONOUS AC CHARACTERISTICS (VCC=1.7~2.0V, TA=-40 to 85C, Maximum Main Clock Frequency=66MHz)
Parameter List Clock Cycle Time Burst Cycle Time Address Set-up Time to ADV Falling(Burst) Address Hold Time from ADV Rising(Burst) ADV Setup Time ADV Hold Time CS Setup Time to Clock Rising(Burst) Burst Operation (Common) Burst End to New ADV Falling Burst Stop to New ADV Falling CS Low Hold Time from Clock CS High Pulse Width ADV High Pulse Width Chip Select to WAIT Low ADV Falling to WAIT Low Clock to WAIT High Chip De-select to WAIT High-Z UB, LB Enable to End of Latency Clock Output Enable to End of Latency Clock UB, LB Valid to Low-Z Output Output Enable to Low-Z Output Burst Read Operation Latency Clock Rising Edge to Data Output Output Hold Burst End Clock to Output High-Z Chip De-select to Output High-Z Output Disable to Output High-Z UB, LB Disable to Output High-Z WE Set-up Time to Command Clock WE Hold Time from Command Clock WE High Pulse Width Burst Write Operation UB, LB Set-up Time to Clock UB, LB Hold Time from Clock Byte Masking Set-up Time to Clock Byte Masking Hold Time from Clock Data Set-up Time to Clock Data Hold Time from Clock
Symbol Min T tBC tAS(B) tAH(B) tADVS tADVH tCSS(B) tBEADV tBSADV tCSLH tCSHP tADHP tWL tAWL tWH tWZ tBEL tOEL tBLZ tOLZ tCD tOH tHZ tCHZ tOHZ tBHZ tWES tWEH tWHP tBS tBH tBMS tBMH tDS tDHC 15 0 7 5 7 5 7 12 7 5 5 1 1 5 5 3 5 5 5 5 5 7 7 5 3
Speed Max 200 2500 10 10 12 12 10 12 12 12 12 -
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Clock Clock ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
- 30 -
Revision 1.0 January 2005
K1B6416B6C
SYNCHRONOUS BURST OPERATION TIMING WAVEFORM
Fig.25 TIMING WAVEFORM OF BASIC BURST OPERATION [Latency=5,Burst Length=4](MRS=VIH)
UtRAM
0 T CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
tADVH tADVS ADV tBEADV tAS(B) tAH(B) tBEADV
Address
Valid
Don't Care
tCSS(B) CS
tBC
Data out
Undefined
DQ0
DQ1
DQ2
DQ3
Data in
D0
D1
D2
D3
Burst Command Clock
Burst Read End Clock Burst Write End Clock
Table 29. BURST OPERATION AC CHARACTERISTICS
Symbol Min T tBC tADVS tADVH 15 5 7 Speed Max 200 2500 ns ns ns ns tAS(B) tAH(B) tCSS(B) tBEADV Units Symbol Min 0 7 5 7 Speed Max ns ns ns ns Units
- 31 -

Valid
D0
Revision 1.0 January 2005
K1B6416B6C
SYNCHRONOUS BURST READ TIMING WAVEFORM
UtRAM
Fig.26 TIMING WAVEFORM OF BURST READ CYCLE(1) [Latency=5,Burst Length=4,WP=Low enable](WE=VIH, MRS=VIH) - CS Toggling Consecutive Burst Read
0 T CLK tADVH tADVS ADV tAS(B) Address
Valid
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
tBEADV tAH(B)
Don't Care Valid
tCSS(B) CS
tBC
tCSHP
tBEL LB, UB tBLZ tOEL OE tOLZ Latency 5 Data out tWL WAIT High-Z tWH tCD
Undefined
tOH DQ0 DQ1 DQ2 DQ3
tWZ
(SYNCHRONOUS BURST READ CYCLE - CS Toggling Consecutive Burst Read) 1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV should be met. 2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge) /WAIT High(tWH) : Data available(driven by Latency-1 clock) /WAIT High-Z(tWZ) : Data don't care(driven by CS high going edge) 3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising. 4. Burst Cycle Time(tBC) should not be over 2.5s.
Table 30. BURST READ AC CHARACTERISTICS(CS Toggling Consecutive Burst)
Symbol Min tCSHP tBEL tOEL tBLZ tOLZ tHZ tCHZ 5 1 1 5 5 Speed Max 12 12 ns clock clock ns ns ns ns tOHZ tBHZ tCD tOH tWL tWH tWZ Units Symbol Min 3 Speed Max 12 12 10 10 12 12 ns ns ns ns ns ns ns Units
- 32 -
tBHZ tOHZ tCHZ tHZ tWL tWH Revision 1.0 January 2005
K1B6416B6C
SYNCHRONOUS BURST READ TIMING WAVEFORM
UtRAM
Fig.27 TIMING WAVEFORM OF BURST READ CYCLE(2) [Latency=5,Burst Length=4,WP=Low enable](WE=VIH, MRS=VIH) - CS Low Holding Consecutive Burst Read
0 T CLK tADVH tADVS ADV tBEADV tAS(B) Address
Valid
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
tAH(B)
Don't Care Valid
tCSS(B) CS tBEL LB, UB tBLZ tOEL OE tOLZ Latency 5 Data out tWL WAIT High-Z
tBC
tCD
Undefined
tOH DQ0 DQ1 DQ2 DQ3
tWH
(SYNCHRONOUS BURST READ CYCLE - CS Low Holding Consecutive Burst Read) 1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV should be met. 2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge) /WAIT High(tWH) : Data available(driven by Latency-1 clock) /WAIT High-Z(tWZ) : Data don't care(driven by CS high going edge) 3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising. 4. The consecutive multiple burst read operation with holding CS low is possible through issuing only new ADV and address. 5. Burst Cycle Time(tBC) should not be over 2.5s.
Table 31. BURST READ AC CHARACTERISTICS(CS Low Holding Consecutive Burst)
Symbol Min tBEL tOEL tBLZ tOLZ tHZ 1 1 5 5 Speed Max 12 clock clock ns ns ns tCD tOH tWL tAWL tWH Units Symbol Min 3 Speed Max 10 10 10 12 ns ns ns ns ns Units
- 33 -

tHZ tAWL tWH Revision 1.0 January 2005
K1B6416B6C
SYNCHRONOUS BURST READ TIMING WAVEFORM
UtRAM
Fig.28 TIMING WAVEFORM OF BURST READ CYCLE(3) [Latency=5,Burst Length=4,WP=Low enable](WE=VIH, MRS=VIH) - Last Data Sustaining
0 T CLK tADVH tADVS ADV tAS(B) Address
Valid
1
2
3
4
5
6
7
8
9
10
11
12
13
14
tAH(B)
Don't Care
tCSS(B) CS tBEL LB, UB tBLZ tOEL OE tOLZ Latency 5 Data out tWL WAIT High-Z
tBC
tCD
Undefined
tOH DQ0 DQ1 DQ2 DQ3
tWH
(SYNCHRONOUS BURST READ CYCLE - Last Data Sustaining) 1. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge) /WAIT High(tWH) : Data available(driven by Latency-1 clock) /WAIT High-Z(tWZ) : Data don't care(driven by CS high going edge) 2. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising. 3. Burst Cycle Time(tBC) should not be over 2.5s.
Table 32. BURST READ AC CHARACTERISTICS(Last Data Sustaining)
Symbol Min tBEL tOEL tBLZ tOLZ 1 1 5 5 Speed Max clock clock ns ns tCD tOH tWL tWH Units Symbol Min 3 Speed Max 10 10 12 ns ns ns ns Units
- 34 -
Revision 1.0 January 2005
K1B6416B6C
SYNCHRONOUS BURST WRITE TIMING WAVEFORM
UtRAM
Fig.29 TIMING WAVEFORM OF BURST WRITE CYCLE(1) [Latency=5,Burst Length=4,WP=Low enable](OE=VIH, MRS=VIH) - CS Toggling Consecutive Burst Write
0 T CLK tADVH tADVS ADV tBEADV tAS(B) Address tCSS(B) CS tBS tBH LB, UB tWEH WE tWES tDS Latency 5 Data in tWL WAIT High-Z tWH tDHC D0 D1 D2 tDHC D3 tWZ tWL tWH Latency 5 D0 tWHP tBMS tBMH
Valid
1
2
3
4
5
6
7
8
9
10
11
12
13
tAH(B)
Don't Care Valid
tBC
tCSHP
(SYNCHRONOUS BURST WRITE CYCLE - CS Toggling Consecutive Burst Write) 1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV should be met. 2. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising. 3. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge) /WAIT High(tWH) : Data available(driven by Latency-1 clock) /WAIT High-Z(tWZ) : Data don't care(driven by CS high going edge) 4. D2 is masked by UB and LB. 5. Burst Cycle Time(tBC) should not be over 2.5s.
Table 33. BURST WRITE AC CHARACTERISTICS(CS Toggling Consecutive Burst)
Symbol Min tCSHP tBS tBH tBMS tBMH tWES tWEH 5 5 5 7 7 5 5 Speed Max ns ns ns ns ns ns ns tWHP tDS tDHC tWL tWH tWZ Units Symbol Min 5 5 3 Speed Max 10 12 12 ns ns ns ns ns ns Units
- 35 -
Revision 1.0 January 2005
K1B6416B6C
SYNCHRONOUS BURST WRITE TIMING WAVEFORM
UtRAM
Fig.30 TIMING WAVEFORM OF BURST WRITE CYCLE(2) [Latency=5,Burst Length=4,WP=Low enable](OE=VIH, MRS=VIH) - CS Low Holding Consecutive Burst Write
0 T CLK tADVH tADVS ADV tBEADV tAS(B) Address
Valid
1
2
3
4
5
6
7
8
9
10
11
12
13
tAH(B)
Don't Care Valid
tCSS(B) CS
tBC tBS tBH tBMS tBMH
LB, UB tWEH WE tWES tDS Latency 5 Data in tWL WAIT High-Z tWH tDHC D0 D1 D2 tDHC D3 tAWL tWH Latency 5 D0 tWHP
(SYNCHRONOUS BURST WRITE CYCLE - CS Low Holding Consecutive Burst Write) 1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV should be met. 2. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising. 3. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge) /WAIT High(tWH) : Data available(driven by Latency-1 clock) /WAIT High-Z(tWZ) : Data don't care(driven by CS high going edge) 4. D2 is masked by UB and LB. 5. The consecutive multiple burst read operation with holding CS low is possible through issuing only new ADV and address. 6. Burst Cycle Time(tBC) should not be over 2.5s.
Table 34. BURST WRITE AC CHARACTERISTICS(CS Low Holding Consecutive Burst)
Symbol Min tBS tBH tBMS tBMH tWES tWEH 5 5 7 7 5 5 Speed Max ns ns ns ns ns ns tWHP tDS tDHC tWL tAWL tWH Units Symbol Min 5 5 3 Speed Max 10 10 12 ns ns ns ns ns ns Units
- 36 -

Revision 1.0 January 2005
K1B6416B6C
SYNCHRONOUS BURST READ STOP TIMING WAVEFORM
UtRAM
Fig.31 TIMING WAVEFORM OF BURST READ STOP by CS [Latency=5,Burst Length=4,WP=Low enable](WE=VIH, MRS=VIH)
0 T CLK tADVH tADVS ADV tBSADV tAS(B) Address
Valid
1
2
3
4
5
6
7
8
9
10
11
12
13
14
tAH(B)
Don't Care Valid
tCSS(B) CS tBEL LB, UB tBLZ OE tOLZ Latency 5 Data tWL tWH WAIT High-Z tOEL tCD
Undefined
tCSHP tCSLH
tOH DQ0 DQ1
tCHZ
tWZ High-Z
(SYNCHRONOUS BURST READ STOP TIMING) 1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBSADV should be met 2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge) /WAIT High(tWH) : Data available(driven by Latency-1 clock) /WAIT High-Z(tWZ) : Data don't care(driven by CS high going edge) 3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising. 4. The burst stop operation should not be repeated for over 2.5s.
Table 35. BURST READ STOP AC CHARACTERISTICS
Symbol Min tBSADV tCSLH tCSHP tBEL tOEL tBLZ tOLZ 12 7 5 1 1 5 5 Speed Max ns ns ns clock clock ns ns tCD tOH tCHZ tWL tWH tWZ Units Symbol Min 3 Speed Max 10 12 10 12 12 ns ns ns ns ns ns Units
- 37 -
tWL Revision 1.0 January 2005
K1B6416B6C
SYNCHRONOUS BURST WRITE STOP TIMING WAVEFORM
UtRAM
Fig.32 TIMING WAVEFORM OF BURST WRITE STOP by CS [Latency=5,Burst Length=4,WP=Low enable](OE=VIH, MRS=VIH)
0 T CLK tADVH tADVS ADV tAS(B) Address
Valid
1
2
3
4
5
6
7
8
9
10
11
12
13
tAH(B)
Don't Care
tBSADV
Valid
tCSS(B) CS tBS tBH LB, UB tWEH tWES tDS Latency 5 Data in tWL tWH WAIT High-Z D0 tCSLH
tCSHP
tWHP
WE
tDHC D1 tWZ tWL High-Z
(SYNCHRONOUS BURST WRITE STOP TIMING) 1. The new burst operation can be issued only after the previous burst operation is finished. 2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge) /WAIT High(tWH) : Data available(driven by Latency-1 clock) /WAIT High-Z(tWZ) : Data don't care(driven by CS high going edge) 3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising. 4. The burst stop operation should not be repeated for over 2.5s.
Table 36. BURST WRITE STOP AC CHARACTERISTICS
Symbol Min tBSADV tCSLH tCSHP tBS tBH tWES tWEH 12 7 5 5 5 5 5 Speed Max ns ns ns ns ns ns ns tWHP tDS tDHC tWL tWH tWZ Units Symbol Min 5 5 3 Speed Max 10 12 12 ns ns ns ns ns ns Units
- 38 -
Latency 5 D0 tWH D1 D2 Revision 1.0 January 2005
K1B6416B6C
SYNCHRONOUS BURST READ SUSPEND TIMING WAVEFORM
UtRAM
Fig.33 TIMING WAVEFORM OF BURST READ SUSPEND CYCLE(1) [Latency=5,Burst Length=4,WP=Low enable](WE=VIH, MRS=VIH)
0 T CLK tADVH tADVS ADV tAS(B) Address
Valid
1
2
3
4
5
6
7
8
9
10
11

tAH(B)
Don't Care
tCSS(B) CS tBEL LB, UB tBLZ tOEL OE tOLZ Latency 5 Data out tWL WAIT High-Z tWH
tBC
tCD
Undefined
tOHZ DQ0 DQ1
tOLZ High-Z DQ1
tOH tHZ DQ2 DQ3 tWZ
(SYNCHRONOUS BURST READ SUSPEND CYCLE) 1. If clock input is halted during burst read operation, the data out will be suspended. During the burst read suspend period, OE high drives data out to high-Z. If clock input is resumed, the suspended data will be out first. 2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge) /WAIT High(tWH) : Data available(driven by Latency-1 clock) /WAIT High-Z(tWZ) : Data don't care(driven by CS high going edge) 3. During suspend period, OE high drives DQ to High-Z and OE low drives DQ to Low-Z. If OE stays low during suspend period, the previous data will be sustained. 4. Burst Cycle Time(tBC) should not be over 2.5s.
Table 37. BURST READ SUSPEND AC CHARACTERISTICS
Symbol Min tBEL tOEL tBLZ tOLZ tCD tOH 1 1 5 5 3 Speed Max 10 clock clock ns ns ns ns tHZ tOHZ tWL tWH tWZ Units Symbol Min Speed Max 12 12 10 12 12 ns ns ns ns ns Units
- 39 -
Revision 1.0 January 2005
K1B6416B6C
TRANSITION TIMING WAVEFORM BETWEEN READ AND WRITE
UtRAM
Fig.34 SYNCH. BURST READ to ASYNCH. WRITE(Address Latch Type) TIMING WAVEFORM
[Latency=5, Burst Length=4](MRS=VIH)
0 T CLK tADVS ADV tBEADV tAS(B) Address
Valid
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20 21
tADVH tADV tAH(A)
tAH(B)
Don't Care
tAS(A)
Valid
tCSS(B) CS
tBC
tCSS(A) tWLRL
tAW tCW tWP
WE tAS tOEL OE tBEL LB, UB tDW Data in Latency 5 Data out High-Z tWL tWH WAIT High-Z High-Z Read Latency 5
(SYNCHRONOUS BURST READ CYCLE) 1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV should be met. 2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge) /WAIT High(tWH) : Data available(driven by Latency-1 clock) /WAIT High-Z(tWZ) : Data don't care(driven by CS high going edge) 3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising. 4. Burst Cycle Time(tBC) should not be over 2.5s. (ADDRESS LATCH TYPE ASYNCHRONOUS WRITE CYCLE - WE controlled) 1. Clock input does not have any affect to the write operation if WE is driven to low before Read Latency-1 clock. Read Latency-1 clock in write timing is just a reference to WE low going for proper write operation.
tBW tDH
Data Valid tCD tOH
DQ0 DQ1 DQ2 DQ3
tHZ High-Z
tWZ
Table 38. BURST READ to ASYNCH. WRITE(Address Latch Type) AC CHARACTERISTICS
Symbol Min tBEADV 7 Speed Max ns tWLRL Units Symbol Min 1 Speed Max clock Units
- 40 -
Revision 1.0 January 2005
K1B6416B6C
TRANSITION TIMING WAVEFORM BETWEEN READ AND WRITE
Fig.35 SYNCH. BURST READ to ASYNCH. WRITE(Low ADV Type) TIMING WAVEFORM
[Latency=5, Burst Length=4](MRS=VIH)
1 T CLK tADVS ADV tAH(B)
Don't Care
UtRAM
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
tADVH
tBEADV
tAS(B) Address
Valid
Valid Address
tCSS(B) CS tBC
tAW tCW tWLRL
tWR
tWP
WE tOEL OE tBEL LB, UB
tAS
tBW
tDW Data in Latency 5 Data out High-Z tWL tWH WAIT High-Z High-Z Read Latency 5
(SYNCHRONOUS BURST READ CYCLE) 1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV should be met. 2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge) /WAIT High(tWH) : Data available(driven by Latency-1 clock) /WAIT High-Z(tWZ) : Data don't care(driven by CS high going edge) 3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising. 4. Burst Cycle Time(tBC) should not be over 2.5s.
tDH
Data Valid tCD tOH
DQ0 DQ1 DQ2 DQ3
tHZ High-Z
tWZ
(LOW ADV TYPE ASYNCHRONOUS WRITE CYCLE - WE controlled) 1. Clock input does not have any affect to the write operation if WE is driven to low before Read Latency-1 clock. Read Latency-1 clock in write timing is just a reference to WE low going for proper write operation.
Table 39. BURST READ to ASYNCH. WRITE(Low ADV Type) AC CHARACTERISTICS
Symbol Min tBEADV 7 Speed Max ns tWLRL Units Symbol Min 1 Speed Max clock Units
- 41 -
Revision 1.0 January 2005
K1B6416B6C
TRANSITION TIMING WAVEFORM BETWEEN READ AND WRITE
UtRAM
Fig.36 ASYNCH. WRITE(Address Latch Type) to SYNCH. BURST READ TIMING WAVEFORM
[Latency=5, Burst Length=4](MRS=VIH)
0 CLK tADVS ADV tAS(A) Address
Valid
1
2
3
4
5
6
7
8
9
10
11 T
12
13
14
15
16
17
18
19
20
tADVH
tADV tAH(A)
Don't Care
tAH(B) tAS(B)
Valid Don't Care
tAW tCSS(A) CS tCW tWLRL WE tAS tWP tCSS(B)
tBC
tOEL OE tBW LB, UB tDW Data in tDH tBEL
Data Valid Latency 5 tCD tOH
DQ0 DQ1 DQ2 DQ3
tHZ
Data out
High-Z Read Latency 5 High-Z
tWL
tWH
tWZ
WAIT
(SYNCHRONOUS BURST READ CYCLE) 1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV should be met. 2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge) /WAIT High(tWH) : Data available(driven by Latency-1 clock) /WAIT High-Z(tWZ) : Data don't care(driven by CS high going edge) 3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising. 4. Burst Cycle Time(tBC) should not be over 2.5s.
(ADDRESS LATCH TYPE ASYNCHRONOUS WRITE CYCLE - WE controlled) 1. Clock input does not have any affect to the write operation if WE is driven to low before Read Latency-1 clock. Read Latency-1 clock in write timing is just a reference to WE low going for proper write operation.
Table 40. ASYNCH. WRITE(Address Latch Type) to BURST READ AC CHARACTERISTICS
Symbol Min tWLRL 1 Speed Max clock Units Symbol Min Speed Max Units
- 42 -
Revision 1.0 January 2005
K1B6416B6C
TRANSITION TIMING WAVEFORM BETWEEN READ AND WRITE
Fig.37 ASYNCH. WRITE(Low ADV Type) to SYNCH. BURST READ TIMING WAVEFORM
[Latency=5, Burst Length=4](MRS=VIH)
0 CLK tADVS tADHP ADV tWC Address
Valid
UtRAM
1
2
3
4
5
6
7
8
9
10
11 T
12
13
14
15
16
17
18
19
20
tADVH
tAH(B) tAS(B)
Valid Don't Care
tAW tCW CS tWLRL tWP WE tAS
tWR
tCSS(B)
tBC
tOEL OE tBW LB, UB tDW Data in tDH tBEL
Data Valid Latency 5 tCD tOH
DQ0 DQ1 DQ2 DQ3
tHZ
Data out
High-Z tWL tWH
tWZ
WAIT
High-Z Read Latency 5
(SYNCHRONOUS BURST READ CYCLE) 1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV should be met. 2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge) /WAIT High(tWH) : Data available(driven by Latency-1 clock) /WAIT High-Z(tWZ) : Data don't care(driven by CS high going edge) 3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising. 4. Burst Cycle Time(tBC) should not be over 2.5s.
(LOW ADV TYPE ASYNCHRONOUS WRITE CYCLE - WE controlled) 1. Clock input does not have any affect to the write operation if WE is driven to low before Read Latency-1 clock. Read Latency-1 clock in write timing is just a reference to WE low going for proper write operation.
Table 41. ASYNCH. WRITE(Low ADV Type) to BURST READ AC CHARACTERISTICS
Symbol Min tWLRL 1 Speed Max clock tADHP Units Symbol Min 5 Speed Max ns Units
- 43 -
Revision 1.0 January 2005
K1B6416B6C
TRANSITION TIMING WAVEFORM BETWEEN READ AND WRITE
Fig.38 SYNCH. BURST READ to SYNCH. BURST WRITE TIMING WAVEFORM
[Latency=5, Burst Length=4](MRS=VIH)
0 T CLK tADVS ADV tAS(B) Address
Valid
UtRAM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20 21
tADVH tBEADV tAH(B)
Don't Care
tAS(B)
Valid
tAH(B)
tCSS(B) CS
tBC tWES
tCSS(B)
tBC
tWEH WE tOEL OE tBEL LB, UB Latency 5 Data in Latency 5 Data out tWL WAIT High-Z High-Z tWH tCD High-Z tOH
DQ0 DQ1 DQ2 DQ3 D0 D1 D2
tBS tBH tDS tDHC
D3
tHZ High-Z tWL tWH tWZ tWZ
(SYNCHRONOUS BURST READ & WRITE CYCLE) 1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV should be met. 2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge) /WAIT High(tWH) : Data available(driven by Latency-1 clock) /WAIT High-Z(tWZ) : Data don't care(driven by CS high going edge) 3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising. 4. Burst Cycle Time(tBC) should not be over 2.5s.
Table 42. BURST READ to BURST WRITE AC CHARACTERISTICS
Symbol Min tBEADV 7 Speed Max ns Units Symbol Min Speed Max Units
- 44 -
Revision 1.0 January 2005
K1B6416B6C
TRANSITION TIMING WAVEFORM BETWEEN READ AND WRITE
Fig.39 SYNCH. BURST WRITE to SYNCH. BURST READ TIMING WAVEFORM
[Latency=5, Burst Length=4](MRS=VIH)
0 T CLK tADVS ADV tAS(B) Address
Valid
UtRAM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20 21
tADVH tBEADV tAH(B)
Don't Care
tAS(B)
Valid
tAH(B)
tCSS(B) CS tWES tWEH WE
tBC
tCSS(B)
tBC
tOEL OE tBS tBH LB, UB Latency 5 Data in
D0 D1 D2
tBEL tDS tDHC
D3
High-Z Latency 5 tCD tOH
DQ0 DQ1 DQ2 DQ3
tHZ
Data out tWL WAIT High-Z tWH
High-Z tWZ tWL tWH
(SYNCHRONOUS BURST READ & WRITE CYCLE) 1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV should be met. 2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge) /WAIT High(tWH) : Data available(driven by Latency-1 clock) /WAIT High-Z(tWZ) : Data don't care(driven by CS high going edge) 3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising. 4. Burst Cycle Time(tBC) should not be over 2.5s.
Table 43. BURST WRITE to BURST READ AC CHARACTERISTICS
Symbol Min tBEADV 7 Speed Max ns Units Symbol Min Speed Max Units
- 45 -
Revision 1.0 January 2005
K1B6416B6C
PACKAGE DIMENSION
54 BALL FINE PITCH BGA(0.75mm ball pitch)
Top View Bottom View B B 6 A #A1 B C D C C1 B/2 Detail A A 0.35/Typ. Y Notes. 1. Bump counts: 54(9 row x 6 column) 2. Bump pitch : (x,y)=(0.75 x 0.75)(typ.) 3. All tolerence are 0.050 unless specified beside figures. 4. Typ : Typical 5. Y is coplanarity: 0.10(Max) E F C1/2 G H J 5 4 B1
UtRAM
Unit: millimeters
3
2
1
Side View
D
C
Min A B B1 C C1 D E E1 E2 Y 5.90 7.90 0.40 0.30 -
Typ 0.75 6.00 3.75 8.00 5.25 0.45 0.90 0.55 0.35 -
Max 6.10 8.10 0.50 1.00 0.40 0.10
0.55/Typ.
- 46 -
Revision 1.0 January 2005
C
E2
E1 E

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